As is known in the art, switching DC-to-DC converters are used to change one DC voltage to another efficiently. There are three basic topologies of switching DC-to-DC converters: step-down (buck), step-up (boost), and step-down/step-up (buck-boost). The buck converter is used to generate a lower dc output voltage, the boost converter is used to generate a higher dc output voltage, and the buck/boost converter is used to generate an output voltage less than, greater than, or equal to the input voltage.
FIG. 1 is schematic of a boost switching DC-to-DC converter of the prior art. The boost switching DC-to-DC converter has an inductor L with a first terminal connected to a first terminal of a power supply voltage source Vin. A second terminal of the power supply voltage source Vin is connected to a ground reference voltage source as a return current path. The associated parasitic resistances RW of the boost switching DC-to-DC converter is shown as a series resistance with the inductor L. The first terminal of the parasitic resistances RW is connected to a second terminal of the inductor L. The second terminal of the parasitic resistances RW is connected to a first terminal of a switch SW and the anode of a diode D. The cathode of the diode D is connected to a first terminal of a filter capacitor C and a first terminal of a load resistance RLOAD. The cathode of the diode D, the first terminal of a filter capacitor C, and the first terminal of a load resistance RLOAD for the output terminal OUT of the boost switching DC-to-DC converter. A duty cycle control signal DC is applied to the control terminal of the switch SW.
The operation of the boost switching DC-to-DC converter begins with the activation of the power supply voltage source Vin. The inductor current IL flows through the inductor L, the parasitic resistances RW, the diode D and the load resistance RL. A portion of the inductor current IL charges the capacitor CL. The switch SW is activated by the control signal DC and the diode D is inversely polarized and nonconducting. Consequently, there is no connection between the power supply voltage source Vin and the load resistance RL and thus the voltage across the load resistance RL is developed by the charge of the capacitor CL. When the switch SW is deactivated, the diode D is polarized to be conducting to allow current to flow from the power supply voltage source Vin to the load resistance RL.
Employing Kirchhoff's voltage and current laws, the output voltage VOUT at the output terminal can be calculated by the equations:
      V    OUT    =            1              1        -        DC              ⁢          V      IN      
Where                VOUT is the voltage at the output terminal OUT.        DC is the duty cycle of the control signal DC.        Vin is the voltage of the power supply voltage source.        
FIG. 2 is schematic of a buck-boost switching DC-to-DC converter of the prior art. The buck-boost switching DC-to-DC converter is capable of scaling the output voltage down with relation to the input voltage or amplifying the output voltage with relation to the input voltage. A buck-boost switching DC-to-DC converter may either invert the output voltage from the input voltage or be non-inverting with the output voltage having the same polarity as the input voltage. The buck-boost switching DC-to-DC converter of FIG. 2 is a non-inverting switching DC-to-DC converter.
The positive terminal of the power supply voltage source Vin is connected to the source of the switching PMOS transistor M1. The negative terminal of the power supply voltage source Vin is connected to the ground reference voltage source. The drain of the switching PMOS transistor M1 is connected to the first terminal of the inductor L and the drain of the switching NMOS transistor M2. The gate of the switching PMOS transistor M1 is connected to the control signal φ1 and the gate of the switching NMOS transistor M2 is connected to the control signal φ2. The source of the NMOS transistor M2 is connected to the ground reference voltage source.
The second terminal of the inductor L is connected to the drains of the NMOS transistor M3 and the PMOS transistor M4. The source of the NMOS transistor M3 is connected to the ground reference voltage source. The source of the PMOS transistor M4 is connected is connected to the first terminal of the filter capacitor CL and first terminal of the load resistor RLOAD. The gate of the NMOS transistor M3 is connected to the control signal (1)3 and the gate of the PMOS transistor M4 is connected to the control signal c4. The source of the PMOS transistor M4, the first terminal of the filter capacitor CL and the first terminal of the load resistor RLOAD form the output terminal OUT of the buck-boost switching DC-to-DC converter. The second terminal of the filter capacitor CL and the second terminal of the load resistor RLOAD are connected to the ground reference voltage source.
The PMOS transistor M1 and the NMOS transistor M3 simultaneously turn on and the NMOS transistor M2 and the PMOS transistor M4 turn off. The power supply voltage source Vin is applied across the inductor L. The inductor current IL increases linearly and the filter capacitor CL provides power to the load resistor RLOAD. When PMOS transistor M1 and the NMOS transistor M3 turn off and the NMOS transistor M2 and the PMOS transistor M4 turn on, the inductor current IL flows through the NMOS transistor M2 and the PMOS transistor M4 to deliver its stored energy to the output terminal OUT. The NMOS transistor M2 and the PMOS transistor M4 turn off, and their body diodes turn on until the control PMOS transistor M1 and the NMOS transistor M3 turn on.
Assuming no power loss in the components of the buck-boost switching DC-to-DC converter, the voltage gain with this control scheme under continuous current mode operation is given by the equation:
      V    OUT    =            DC              1        -        DC              ⁢          V      IN      
Where                VOUT is the voltage at the output terminal OUT.        DC is the duty cycle of the control signal DC.        Vin is the voltage of the power supply voltage source.        
For the duty cycle DC of 50%, the output voltage VOUT is equal to the input voltage VIN. The output voltage VOUT is lower than the input voltage VIN for a duty cycle DC less than 50%, and the output voltage VOUT is higher than the input voltage VOUT for the duty cycle DC greater than 50%.
The description above does not take the parasitic resistances RW into account. In both boost and buck-boost switching DC-to-DC converters, the gain or the ratio of the output voltage VOUT to the input voltage VIN (Vout/Vin) is inversely proportional to (1-D) which states voltage VOUT will reach infinity when the duty cycle DC=1.
The parasitic resistance RW is the total resistance in series with the inductor L. The parasitic resistance RW includes:                1. The equivalent series resistance (ESR) of the inductor L,        2. The parasitic resistances due to on-chip and off-chip connections,        3. The on-resistance due to diode D of FIG. 1 or pass PMOS transistor M4 of FIG. 2 multiplied by one minus the duty cycle (1-DC),        4. The resistance of switch SW of FIG. 1 or the NMOS transistor M3 multiplied by the duty cycle DC, and        5. In buck-boost switching DC-to-DC converter, the resistance of PMOS transistor M1 of FIG. 2 when the converter is working in boost mode.        
FIG. 3 is a plot of the effect of inductor winding resistance on the voltage gain of the boost switching DC-to-DC converter versus duty cycle of the prior art as shown in slide 25 of “Advanced Engineering Course on Power Management”, Richard Redl, Lausanne, Switzerland, Aug. 26-30, 2013. The plot 5 illustrates the gain of the boost switching DC-to-DC converter versus the duty cycle DC illustrates the rise in the gain toward infinity with the duty cycle DC toward infinity with the parasitic resistance RW equal to zero. The plots 10, 15, 20, and 25 show the rise of the gain of the boost switching DC-to-DC converter to the peak values 30 where the slope becomes negative.
If the value of the duty cycle DC reaches right side or negative slope region beyond the peak 30, the output voltage VOUT will begin falling and the control loop of the boost switching DC-to-DC converter will increase the duty cycle DC further. This results in positive feedback increasing the duty cycle DC and eventually duty cycle DC will be stuck at 100% and the output voltage VOUT will be some low voltage. This problem becomes more significant in buck-boost switching DC-to-DC converter where the pass PMOS transistor M1 and PMOS transistor M4 of FIG. 2 are in series with the inductor for any given cycle.
One practical solution for this issue of the prior art is setting a limit for the duty cycle DC (e.g. limiting the duty cycle DC at 60%, such that it will not increase further). The duty cycle limit Dlimit is estimated considering the worst case scenario such as a minimum voltage level input power supply voltage source Vin, worst case temperature, maximum on resistance of the pass PMOS transistor M1, minimum load resistance RLOAD, etc. Setting a limit for the duty cycle DC based on worst case conditions also limits the operation of the switching converter in optimal conditions, as the duty cycle DC cannot exceed the duty cycle limit Dlimit in cases where it could be beneficial for system performance to utilize higher values of the duty cycle DC. This especially true when the switching DC-to-DC converter should utilize higher values of the duty cycle DC at low load conditions.